Search results for "Digital signal processor"
showing 10 items of 12 documents
Implementation of pattern recognition algorithm based on RBF neural network
2002
In this paper, we present implementations of a pattern recognition algorithm which uses a RBF (Radial Basis Function) neural network. Our aim is to elaborate a quite efficient system which realizes real time faces tracking and identity verification in natural video sequences. Hardware implementations have been realized on an embedded system developed by our laboratory. This system is based on a DSP (Digital Signal Processor) TMS320C6x. The optimization of implementations allow us to obtain a processing speed of 4.8 images (240x320 pixels) per second with a correct rate of 95% of faces tracking and identity verification.
Muon identification with the ATLAS Tile Calorimeter Read-Out Driver for Level-2 trigger purposes
2008
The Hadronic Tile Calorimeter (TileCal) at the ATLAS experiment is a detector made out of iron as passive medium and plastic scintillating tiles as active medium. The light produced by the particles is converted to electrical signals which are digitized in the front-end electronics and sent to the back-end system. The main element of the back-end electronics are the VME 9U Read-Out Driver (ROD) boards, responsible of data management, processing and transmission. A total of 32 ROD boards, placed in the data acquisition chain between Level-1 and Level-2 trigger, are needed to read out the whole calorimeter. They are equipped with fixed-point Digital Signal Processors (DSPs) that apply online …
Portable Video Supercomputing
2004
As inexpensive imaging chips and wireless telecommunications are incorporated into an increasing array, of portable products, the need for high efficiency, high throughput embedded processing will become an important challenge in computer architecture. Videocentric applications, such wireless videoconferencing, real-time video enhancement and analysis, and new, immersive modes of distance education, will exceed the computational capabilities of current microprocessor and digital signal processor (DSP) architectures. A new class of embedded computers, portable video supercomputers, will combine supercomputer performance with the energy efficiency required for deployment in portable systems. …
Design And Characterization Of Automated Color Sensor System
2017
Abstract The paper presents a color sensor system that can process light reflected from a surface and produce a digital output representing the color of the surface. The end-user interface circuit requires only a 3-bit pseudo flash analog-to-digital converter (ADC) in place of the conventional/typical design comprising ADC, digital signal processor and memory. For scalability and compactness, the ADC was designed such that only two comparators were required regardless of the number of color/wavelength to be identified. The complete system design has been implemented in hardware (bread board) and fully characterized. The ADC achieved less than 0.1 LSB for both INL and DNL. The experimental r…
Design and Low-Cost Implementation of an Optimally Robust Reduced-Order Rotor Flux Observer for Induction Motor Control
2007
The aim of this paper is to design and analyze reduced-order observers of the rotor flux of induction motors. The design is carried out in two steps. In the first step, a boundary of the stability region of the observation error is obtained corresponding to a chosen Lyapunov function. In the second step, the boundary is translated into a performance index that is minimized with respect to stator and rotor resistance variations and differences of voltages supplying the motor and those supplying the observer in order to obtain the largest stability region. Implementation of the observer on a low-cost fixed-point digital signal processor using look-up tables is described. Experimental results …
Implementation and Performance of the Signal Reconstruction in the ATLAS Hadronic Tile Calorimeter
2012
AbstractThe Tile Calorimeter (TileCal) for the ATLAS experiment at the CERN Large Hadron Collider (LHC) is currently taking data with proton-proton collisions. The Tile Calorimeter is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are read-out by wavelength shifting fibers coupled to photomultiplier tubes (PMT). The analogue signals from the PMTs are amplified, shaped and digitized by sampling the signal every 25ns. The TileCal front-end electronics allows to read-out the signals produced by about 10000 channels measuring energies ranging from ∼30 MeV to ∼2 TeV. The read-out system is designed to reconstruct the data in real-time fulfilli…
The ATLAS TileCal read-out drivers signal reconstruction
2009
TileCal is the hadronic calorimeter of the ATLAS experiment at the LHC collider at CERN. The Read-Out Drivers (ROD) are the core of the off-detector electronics. The main components of the RODs are the Digital Signal Processor (DSP) placed on the Processing Unit (PU) dautherboards. This paper describes the DSP code and its performance with calibration and real data. The code is divided into two different parts: the first part contains the core functionalities and the second one the reconstruction algorithms. The core acts as an operating system and it controls the configuration, the data reception, transmission, online monitoring and the synchronization between front-end data and the Trigge…
DSP Online Algorithms for The ATLAS TileCal Read-Out Drivers
2007
TileCal is the hadronic tile calorimeter of the ATLAS experiment at LHC/CERN. The central element of the back-end system of the TileCal detector is the read-out driver (ROD).The main components of the TileCal ROD are the digital signal processors (DSPs) placed on the processing unit (PU) daughterboards. This paper presents a detailed description of the code developed for the DSPs. The code is divided into two different parts: the first part contains the core functionalities and the second part the reconstruction algorithms. The core acts as an operating system and controls configuration, data reception and transmission and synchronization between front-end data and the timing, trigger and c…
A novel four-quadrant power supply for low-energy correction magnets
2003
Abstract This paper describes an efficient power supply to feed low-energy correction magnets in particle accelerator applications, where a controlled current with trapezoidal profile and four-quadrant operation is needed. The selected design is based on an AC–DC matrix converter topology, which uses the Space Vector Modulation (SVM) technique to obtain a near unity power factor at the AC input and output DC current regulation. This topology allows performing high-frequency isolation, while four-quadrant operation is maintained, and reducing volume and weight as compared with the classical thyristor (SCR)-based technology. Control tasks are implemented on an all-digital control card: output…
A new heterogeneous and reconfigurable architecture for image analysis
1993
In the paper a new architecture for image analysis: HERMIA (Heterogeneous and Reconfigurable Machine for Image Analysis) is presented. It has bt:en developed at the University of Palermo, inside the Progetto Finalizzato of the ltalian Council of Researches (CNR): Sistemi informatici e Calcolo Parallelo. The architecture of the HERMIA-machine is reconfigurable, moreover the integration of heterogeneous module, oriented to the solution of specific problems, allows to salve complex problems by search of optimal strategies. Signa! processing units allows the user to handle and integrate multi-sensors signals (from video, scanner, music recorder). Here the generai architecture, the hardware impl…